High resolution arbitrary waveform generators (AWGs) are employed in electronic applications to provide arbitrary high frequency waveforms. Agile high resolution arbitrary waveform generators deliver fast switching of arbitrary waveforms. One way to implement a high frequency is to use a Direct Digital Synthesis (DDS) for creating arbitrary waveforms from a single, fixed-frequency reference clock. A more common implementation for an AWG is where a memory filled with waveform parameters is directly routed to a digital-to-analog converter (DAC). This direct memory approach, which bypasses the DDS, allows for much more complex waveforms to be implemented, such as those that involve feedback where the value of waveform samples depend on prior waveform samples. The feedback loop or any other formulation for the waveform samples are computed in non-real time, such as on a computer, and then loaded into the memory of the AWG device.
FIG. 1 illustrates an exemplary conventional waveform generation circuit that includes an input signal 102, a phase accumulator 108, a waveform look-up table 106, a reference clock 110, a digital-to-analog converter (DAC) 112 and a filter 114. The phase accumulator and the waveform look-up table form a DDS circuit 104 for producing a high frequency digital signal that is converted to a high frequency analog signal by the DAC 112. The waveform look-up table is programmable by storing binary data for every combination of input data provided by the phase accumulator 108. The DDS output waveform is then written to the look-up table 106. In a DDS bypass mode, the look-up table memory 106 stores the computed waveform values and the values are streamed directly to the DAC. In this mode, the input from the phase accumulator 108 is disabled.
Delta-sigma modulation is a method for encoding analog signals into digital signals, for example, in an analog-to-digital converter (ADC). This modulation scheme is also used to convert high bit-count, low-frequency digital signals into lower bit-count, higher-frequency digital signals as part of a process to convert digital signals into analog, for example, in a DAC. In delta modulation stage of a delta-sigma modulation, the change in the signal (i.e., delta) is encoded (instead of the absolute value). The output is a stream of pulses, as opposed to a stream of numbers in pulse code modulation (PCM). In delta-sigma modulation, the accuracy of the modulation is improved by passing the digital output through a 1-bit DAC and adding (i.e., sigma) the resulting analog signal to the input signal before delta modulation to reduce the error introduced by the delta-modulation.
A delta-sigma ADC typically encodes an analog signal using high-frequency delta-sigma modulation, and then applies a digital filter to form a higher-resolution but lower sample-frequency digital output. A delta-sigma DAC encodes a high-resolution digital input signal into a lower-resolution but higher sample-frequency signal and then smoothen it with an analog filter. In both cases, the temporary use of a lower-resolution signal simplifies circuit design and improves efficiency.
FIG. 2 illustrates a typical delta-sigma modulator. As shown, the delta-sigma modulator comprises a feedback 1-bit DAC 216, a loop transfer function (i.e., frequency response of output signal 215/input signal 202) that acts as a filter and is made up of a delay implemented in the feedback DAC 216, delay or gain implemented in the feedback lines 217 and 203 and a quantizer 212. This way, an input signal 202 is quantized by the quantizer 212, resulting in some quantization error. This quantization error is then fed back and subtracted from the input signal 202 to correct the quantization error. After the quantizer 212, the quantization error is fed back through signal line 215. In a receive mode of the system where the input signal 202 is analog and the quantizer converts the analog signal to a digital signal, the feedback continues through the DAC 216 to be fed back through signal lines 217, 209 and 203.
The order of the filter is set to be the number of feedback loop paths in the summation block. In general, the higher the order of the delta-sigma modulator, the more quantization error can be removed and thus the higher the final dynamic range. However, a higher order filter results in more circuit complexity (e.g., more feedback loops). FIG. 2 depicts two feedback loops comprising signal path 217 to signal path 209 and into a summation circuit 208, and signal path 217 to signal path 203 and into the summation circuit 204. The input 202 to the modulator goes through several integrators 206 and 210 and summation circuits 204 and 208. These integrators 206 and 210 serve to integrate or sum successive values of the input signal 202. The integration time is one of the key parameters that define the modulator performance. Longer integration times result in larger gain, but also can result in lower sensitivity to error.
The integrators 206 and 210 often serve to create an average value from the input signal 202. A longer integration time in integrators 206 and 210 are effective in, for example, dampening out very high frequency oscillations that are undesirable. The summation blocks 204 and 208 serve to subtract out error that is relayed through the feedback loop. A (digital) filter 214 is used to perform post processing on the quantized signal, and the output of the digital filter 214 represents the output of the delta-sigma modulator. Typical filtering operations include digital down conversion and low pass filtering to decimate the signal to a lower sampling rate.
In some cases, the input signal 202 is a digital signal and the quantizer 212 converts the digital input to an analog signal. In these cases, the filter 214 would be an analog filter and the feedback can be performed digitally so the DAC 216 would not be required.
A single-bit delta-sigma modulator is popular primarily because of the inherent linearity of a single-bit feedback DAC. On the other hand, a single-bit quantizer makes the delta-sigma modulator a non-linear system. The single-bit delta-sigma modulator consequently produces very large tones near the half of a sampling frequency, also referred to as idle tones, as a result of limited cycles. The idle tones are particularly relevant, if another signal near the half of the sampling frequency interferes with a bit stream of the delta-sigma modulator. In this case, a tone gets folded down, for example, in the baseband.
A phase lock loop (PLL) is used in a reference clock generator, such as the reference clock 110 in FIG. 1, to generate an output signal, the phase of which is related to the phase of the input signal 102. A typical PLL includes a variable frequency oscillator and a phase detector in a feedback loop. The oscillator generates a periodic signal, and the phase detector compares the phase of that signal with the phase of the input periodic signal, adjusting the oscillator to keep the phases matched. In addition to synchronizing signals, a PLL can track an input frequency, or it can generate an output signal with a frequency that is a multiple of the input signal frequency, which are used for clock synchronization, signal demodulation, and frequency synthesis.
In a direct radio frequency (RF) signal conversion, the conversion of the modulated signal to a baseband signal is performed in a single frequency conversion. This avoids the complexity of the superheterodyne that performs two (or more) frequency conversions, intermediate frequency (IF) stage(s). In the direct RF signal conversion, the received RF signal is fed directly into a frequency mixer, where the frequency of the local oscillator is not offset from, but identical to, the received signal's frequency. The result is a demodulated output similar to output of a superheterodyne receiver using synchronous detection following an IF stage. However, direct RF conversion is expensive for arbitrary frequencies and bandwidths.
Prior approaches use a variable sampling frequency, which requires resetting the PLL also known as the reference clock in the circuit, such as resetting the reference clock 110 shown in FIG. 1, which inhibits real-time updates and thus diminishes real-time performance. Another prior approach for an RF application for Long Term Evolution (LTE) signals relies on a fixed sampling frequency (Fs) to produce a bandpass signal at Fs/4. However, this approach is not frequency agile in software.
Therefore, there is a need for a frequency agile waveform generator whose coefficients are software defined to provide a variable approach in software for generating the parameters (e.g., passband frequency, bandwidth, etc.) in real-time.